1. Field of the Invention
The present invention relates to a digital PLL circuit, for recovering a clock signal, which is used to regenerate data from an analog baseband signal whose frequency band is limited due to removal of high-frequency components.
2. Description of the Related Art
A digital PLL circuit for recovering a clock signal from an analog baseband signal is disclosed in, for example, Japanese Unexamined Patent Publication No. 8-31110. This PLL circuit has an A/D converter that samples the baseband signal having a limited frequency band. The A/D converter transfers the sampled data to a delay circuit. The delay circuit has "N-1" delay stages to delay the sampled data by N (N.gtoreq.2) periods of the recovered clock signal. The A/D converter and the delay circuit provide N pieces of digital data in total, which are converted into N binary bits. The N binary bits are transferred to a logic operation unit, which carries out a logic operation on them. Among the N binary bits, two are supplied to an arithmetic operation unit, which calculates the difference or sum of the two and provides the result to a latch circuit. The latch circuit latches the result depending on the output of the logic operation unit and provides a signal for controlling the oscillation frequency of an oscillator. The oscillator provides the recovered clock signal used to regenerate data. The logic operation unit detects a zero crossing point, or in other words, a transition-level crossing point, at which the baseband signal crosses a transition level, in the output of the A/D converter according to the N binary bits and determines whether the inclination of the baseband signal at the crossing point is positive or negative. The polarity of the output of the arithmetic operation unit may be inverted according to the inclination. The logic operation unit controls the latch circuit according to the detected crossing point. The logic operation unit also controls the polarity of the output of the arithmetic operation unit according to whether the inclination is positive or negative. With these operations, the PLL circuit synchronizes the phase of the recovered clock signal with that of the baseband signal.
This prior art, as will be explained later in detail, is incapable of adjusting a frequency if a large phase difference is involved. This results in elongating a lockup time.
An offset involved in the analog baseband signal causes an error in the N binary bits, to destabilize the operation of the PLL circuit.